SysML Plugin TWRT Documentation

This page describes how to simulate Signal Processor example model in Simulink. Learn more about Signal Processor sample model >>

You can find the Signal Processor sample model in:

  • the modeling tool: Welcome window > Samples > Simulink and Modelica Transformation > SignalProcessor.
  • the Installation directory: <modeling tool installation directory>\samples\SysML\Simulink and Modelica Transformation\Signal Processor.


To simulate the TestBed model

  1. Export the TestBed Block to Modelica file. How to >>
  2. Make sure the Dymola tool is installed. How to >>
  3. Start the Dymola.
  4. Click File > Open > Load... and select saved TestBed.mo file from your file directory. A TestBed model is displayed in the Package Browser.
  5. In the Graphics tab toolbar, click  to check model for syntax and semantic errors. The result panel displays whether the model is ready for simulation.
  6. Setup the simulation run for the model:
        a. Select the Simulation tab and in its toolbar click .
        b. In the Simulation Setup dialog, specify the Start time value to 0 and the Stop time value to 20 seconds (or any other reasonable amount of time, for this model 20 seconds should be enough) .
        c. Click OK.

  7. In the Simulation tab toolbar, click .

    When the simulation is completed, the output is displayed in the panel at the bottom and the TestBed variables are displayed in the Variable Browser.

  8. To see the input and output of the SourceToSinkModel, variables from the Variable Browser must be chosen. Selecting SourceToSinkModel > SourceToSink > inputSignal > y will display the input on the plotting window. Selecting SourceToSinkModel > SourceToSink > scopeSignal > output will display the simulation’s output on the plotting window.




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